FMA Unit 5. 3 8255 - PPI_Functional Block Diagram

8255 Functional Block Diagram

1.               Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is transmitted or received by the buffer as per the instructions by the CPU. Control words and status information is also transferred using this bus.

2.               Read/Write Control Logic

This block is responsible for controlling the internal/external transfer of data/control/status word. It accepts the input from the CPU address and control buses, and in turn issues command to both the control groups.

3.               Ports of 8255

• Port A and Port B: It contains one 8-bit output latch/buffer and one 8-bit input buffer.
• Port C: It can be split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) by the control word.

4.               Group A and Group B Control

• The three ports are further divided into two groups.
• Group A send the control signals to PORT A and upper PORT C. Group B send the control signals to PORT B and lower PORT C.
• These two groups can be programmed in three different modes, i.e. mode 0, Mode 1 and Mode 2.