FMA Unit 4.1 Interrupt

8051 Interrupts

Interrupts are the events that temporarily suspend the main program, pass the control to the external sources and execute their task. It then passes the control to the main program where it had left off.

Interrupts are of different types like software and hardware, maskable and non-maskable, fixed and vector interrupts, and so on. Interrupt Service Routine (ISR) comes into the picture when interrupt occurs, and then tells the processor to take appropriate action for the interrupt, and after ISR execution, the controller jumps into the main program.

Interrupt Structure

Upon ‘RESET’ all the interrupts get disabled, and therefore, all these interrupts must be enabled by software. In all these five interrupts, if anyone or all are activated, this sets the corresponding interrupt flags as shown in the figure.

All these interrupts can be set or cleared by bit in some special function register that is Interrupt Enabled (IE), and this in turn depends on the priority, which is executed by IP interrupt priority register.

 

 

A.     IE register (Interrupt Enable Register)

IE register is used to enable/disable interrupt sources.

      

Bit 7 – EA: Enable All Bit

                              1 = Enable all interrupts

                    0 = Disable all interrupts

Bit 6,5 – Reserved bits

Bit 4 – ES: Enable Serial Interrupt Bit

                   1 = Enable

                   0 = Disable

Bit 3 – ET1: Enable Timer 1 Interrupt Bit

          1 = Enable

                             0 = Disable

Bit 2 – EX1: Enable External 1 Interrupt Bit

                             1 = Enable

                   0 = Disable

Bit 1 – ET0: Enable Timer 0 Interrupt Bit

                   1 = Enable

                   0 = Disable

Bit 0 – EX0: Enable External 0 Interrupt Bit

                             1 = Enable

                   0 = Disable

B.    Interrupt priority

In the table, interrupts priorities upon reset are shown. As per 8051 interrupt priorities, lowest priority interrupts are not served until microcontroller is finished with higher priority ones. In a case when two or more interrupts arrives microcontroller queues them according to priority.

Priority	Intr. bit / flag
1	INT0
2	TF0
3	INT1
4	TF1
5	(TI/RI)

B.1. IP Register (Interrupt priority register)

8051 has interrupt priority register to assign priority to interrupts.  

     

Bit 7,6,5 – Reserved bits.

Bit 4 – PS: Serial Interrupt Priority Bit

            1 = Assign high priority.

            0 = Assign low priority.

Bit 3 and Bit 1 – PT: Timer 1 / Timer 0 Interrupt Priority Bit         

            1 = Assign high priority.

            0 = Assign low priority.

Bit 2 and Bit 0 – PX: External Interrupt 1 / External Interrupt 0 Priority Bit    

            1 = Assign high priority.

            0 = Assign low priority.

Types of Interrupts in 8051 Micro controller

When an interrupt occurs, the micro-controller executes the interrupt service routine so that memory location corresponds to the interrupt that enables it.

The Interrupt corresponding to the memory location is given in the interrupt vector table below.

Interrupt	Flag	Interrupt vector address
Reset	-	0000H
INT0 (Ext. int. 0)	IE0	0003H
Timer 0	TF0	000BH
INT1 (Ext. int. 1)	IE1	0013H
Timer 1	TF1	001BH
Serial	TI/RI	0023H

1             1.  Reset

          Reset is the highest priority interrupt, upon reset 8051 microcontroller start                    executing code from 0x0000 address.

2             2. Internal interrupt (Timer Interrupt) (TF0 and TF1)

8051 has two internal interrupts namely timer0 and timer1. Whenever timer overflows, timer overflow flags (TF0/TF1) are set. Then the microcontroller jumps to their vector address to serve the interrupt. For this, global and timer interrupt should be enabled.

3             3. Serial interrupt (RI/TI)

8051 has serial communication port and have related serial interrupt flags (TI (Transfer Interrupt) /RI (Receiver Interrupt)).

When the last bit (stop bit) of a byte is transmitted, TI serial interrupt flag is set and when last bit (stop bit) of receiving data byte is received, RI flag get set.

4. External interrupts

8051 has two external interrupt INT0 and INT1. External interrupt has two types of activation level

1.                 Edge triggered (Interrupt occur on rising/falling edge detection)

2.                 Level triggered (Interrupt occur on high/low-level detection)

Whenever a low level / falling edge is detected on the INT0/INT1 pin while global and external interrupts are enabled, the controller jumps to interrupt service routine (ISR) to serve interrupt.

4.1.    TCON: Timer/ counter Register

Bit 3 and Bit 1 - IE:      

       External Interrupt 1/ External Interrupt 0 edge flag, set by hardware when interrupt on INT1 / INT0 pin occurred and cleared by hardware when interrupt get processed.

Bit 2 and Bit 0 - IT1:

 This bit selects external interrupt event type on INT1 / INT0 pin,

       1= sets interrupt on falling edge

       0= sets interrupt on low level